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STA020
96kHz DIGITAL AUDIO INTERFACE TRANSMITTER
MONOLITHIC DIGITAL AUDIO INTERFACE TRANSMITTER 3.3V SUPPLY VOLTAGE SUPPORTS: - AES/EBU, IEC 958, - S/PDIF, & EIAJ CP-340 - Professional and Consumer Formats PARITY BITS AND CRC CODES GENERATED TRANSPARENT MODE ALLOWS DIRECT CONNECTION OF STA020 AND STA120 DESCRIPTION The STA020 is a monolithic CMOS device which encodes and transmits audio data according to the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 interface standards. It supports 96kHz sample rate operation The STA020 accepts audio and digital data which is then multiplexed, encoded and driven onto a cable. The audio serial port is double buffered and caBLOCK DIAGRAM
SDIP24
STA020
M0 23 SCK FSYNC SDATA 6 7 8
M1
C U V
w
10 11 9
w
w
AUDIO SERIAL PORT
t a .D
M2 22 21
S a
VD+ 19
e h
GND 18
pable of supporting a wide variety of formats. The STA020 multiplexes the channel, user, and validity data directly from serial input pins with dedicated input pins for the most important channel status bits.
U t4 e
MCK 5
ORDERING NUMBERS: STA020D
.c
m o
SO24
RST 16
20 MUX DIFFERENTIAL
TXP
17
TXN
REGISTERS 7
15 DEDICATED CHANNEL CBL STATUS BUS
24 TRNPT
D97AU599A
September 2002
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STA020
ABSOLUTE MAXIMUM RATINGS
Symbol VD+ VIND Tamb Tstg DC Power Supply Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature Parameter Value 4 -0.3 to VD+ 0.3 -20 to +85 -40 to 150 Unit V V C C
RECOMMNDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground)
Symbol V D+ Tamb Parameter DC Voltage Ambient Operating Temp. Test Condition Min. 3 0 Typ. 3.3 25 Max. 3.6 70 Unit V C
PIN CONNECTION
C7/C3 PRO C1/FC0 C6/C2 MCK SCK FSYNC SDATA V C/SBF U C9/C15
1 2 3 4 5 6 7 8 9 10 11 12
D97AU608A
24 23 22 21 20 19 18 17 16 15 14 13
TRNPT/FC1 M0 M1 M2 TXP VD+ GND TXN RST CBL/SBC EM0/C9 EM1/C8
PINS DESCRIPTION
N. Name Function Power Supply Connections 18 GND Ground. 19 VD+ Positive Digital Power. Nominally +3.3V. Audio Input Interface 6 SCK Serial Clock. Serial clock for SDATA pin which can be configured (via the M0, M1 and M2 pins) as an input or output and can sample data on the rising or falling edge.As an output, SCK will contain 32 clocks for every audio sample. 7 FSYNC Frame Sync. Delineates the serial data and may indicate the particular channel, left or right and may be an input or output. The format is based on M0, M1 and M2 pins.
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STA020
PINS DESCRIPTION (continued)
N. 8 Name SDATA Function Serial Data. Audio data serial input pin. Serial Port Mode Select. Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. Channel Status Bit 7/Channel Status Bit 3. In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the inverse of channel status bit 3, C7/C3 are ignored in Transparent Mode. Professional/Consumer Select. Selects between professional mode (PRO low) and consumer mode (PRO high). This pin defines the functionality of the channel status parallel pins. PRO is ignored in Transparent Mode. Channel Status Bit 1/Frequency Control 0. In professional mode, C1 is the inverse of channel status bit 1. In consumer mode, FC0 and FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When FC0 and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent Mode. Channel Status Bit 6/Channel Status Bit 2. In professional mode, C6 is the inverse of channel status bit 6. In consumer mode, C2 is the inverse of channel status bit 2. C6/C2 are ignored in Transparent Mode. Validity. Validity bit serial input port. This bit is defined as per the digital audio standards wherein V = 0 signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio signal is not suitable for conversion to analog, i.e. invalid. Channel Status Serial Input/Subcode Frame Clock. In professional and consumer modes this pin is the channel status serial input port. In CD mode this pin inputs the CD subcode frame clock. User Bit. User bit serial input port. Channel Status Bit 9/Channel Status Bit 15. In professional mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). In consumer mode, C15 is the inverse of channel status bit 15 (bit 7 of byte 1). C9/C15 are ignored in Transparent Mode. Emphasis 1/Channel Status Bit 8. In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer mode, C8 is the inverse of channel status bit 8 (bit 0 of byte 1). EM1/C8 are ignored in Transparent Mode. Emphasis 0/Channel Status Bit 9. In professional mode, EM0 and EM1 encode channel status bits 2, 3 and 4. In consumer mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). EM0/C9 are ignored in Transparent Mode. Channel Status Block Output/Subcode Bit Clock. In professional and consumer modes, the channel status block output is high for the first 15 bytes of channel status. In CD mode, this pin outputs the subcode bit clock. Master Reset. When low, all internal counters are reset. Transparent Mode/Frequency Control 1. In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting TRNPT high, allows the STA020 to be connected directly to an STA120. In transparent mode, CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and FC1 are encoded versions of channel status bits 24 and 25. When FC0 and FC1 are both high, CD mode is selected.
21, M0, M1, M2 22,23 Control Pins 1 C7/C3
2
PRO
3
C1/FC0
4
C6/C2
9
V
10
C/SBF
11 12
U C9/C15
13
EM1/C8
14
EM0/C9
15
CBL/SBC
16 24
RST TRNPT/FC1
Transmitter Interface 5 MCK Master Clock. Clock input at 128x the sample frequency which defines the transmit timing. In trasparent mode MCK must be 256 Fs. 20, 17 TXP, TXN Differential Line Drivers.
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STA020
DIGITAL CHARACTERISTICS (Tamb = 25C; VD+ = 3.3V 10%)
Symbol VIH V IL VOH V OL Iin MCK Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current Master Clock frequency Master Clock Duty Cycle (Note 1) (high time/cycle time) 40 IO = 200A IO = 3.2mA 1.0 Test Condition Min. 2.0 -0.3 VDD-1.0 0.4 10 26 60 Typ. Max. VDD+0.3 +0.8 Unit V V V V A MHz %
Note 1: MCK must be 128x the input word rate, except in Transparent Mode where MCK is 256x the input word rate.
Figure 1. STA020 Professional & Consumer Modes Typical Connection Diagram.
EXTERNAL CLOCK
+3.3V
MCK FSYNC AUDIO DATA PROCESSOR SCK SDATA 7 6 8 5 19
VD+ 18 24 GND TRNPT
0.1F
CBL C CONTROLLER or UNUSED U V RST CHANNEL STATUS BITS CONTROL
23 15 10 11 9 16 20 22
M0 M1 M2 SERIAL PORT MODE SELECT
STA020
21
TXP TRANSMITTER CIRCUIT
8 DEDICATED C.S. BITS
17
TXN
D97AU600A
Figure 2. STA020 Typical Connection Diagram.
EXTERNAL CLOCK
+5V
FSYNC AUDIO DATA PROCESSOR SCK SDATA V DECODER SUBCODE PORT SBF U SBC
MCK 7 6 8 9 10 11 15 5 19
VD+ 18 GND
0.1F
23 22
M0 M1 M2 SERIAL PORT MODE SELECT
STA020
21
RESET CONTROL
RST
16
20
TXP TRANSMITTER CIRCUIT
17 CHANNEL STATUS BITS CONTROL 8 DEDICATED C.S. BITS
TXN
D99AU989B
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STA020
GENERAL DESCRIPTION The STA020 is a monolithic CMOS circuit that encodes and transmits audio and digital data according to the AES/EBU, IEC 958, S/PDIF, and EIAJ CP-340 interface standards. The chip accepts audio and control data separately; multiplex and biphase-mark encode the data internally and drive it, directly or through a transformer, to a transmission line. The STA020 has dedicated pins for the most important control bits and a serial input port for the C, U and V bits. Line Drivers The differential line drivers for STA020 are low skew, low impedance, differential outputs capable of driving 110Ohm transmission lines. (RS422 line driver compatible). They can also be disabled by resetting the device (RST = low). STA020 DESCRIPTION The STA020 accepts 16 to 24-bit audio samples through a serial port configured in one of seven formats; provides several pins dedicated to particular channel status bits and allows all channel status, user and validity bits to be serially input through port pins. This data is multiplexed, the parity bit is generated and the bit stream is biphase-mark encoded and driven through an RS422 line driver. The STA020 operates as a professional or consumer interface transmitter selectable by pin 2, PRO. As a professional interface device, the dedicated channel status input pins are defined according to the professional standard, and the CRC code (C.S. byte 23) can be internally generated. As a consumer device, the dedicated channel status input pins are defined according to the consumer standard. A submode provided under the consumer mode is compact disk, CD, mode. When transmitting data from a compact disk, the CD subcode port can accept CD subcode data, extract channel status information from it, and transmit it as user data. The master clock , MCK, controls timing for the entire chip and must be 128xFs. As an example, if stereo data is input to the STA020 at 44.1kHz, MCK input must be 128 times that or 5.6448MHz.
Audio Serial Port The audio serial port is used to enter audio data and consists of three pins: SCK, SDATA and FSYNC, SCK clocks in SDATA, which is double buffered, while FSYNC delineates the audio samples and may indicate the particular channel, left or right. To support many different interfaces, M2, M1 and M0 select one of seven different formats for the serial port. The coding is shown in Table 3 while the formats are shown in Figure 3. Format 0 and 1 are designed to interface with Crystal ADCs. Format 2 communicates with Motorola and TI DSPs. Format 3 is reserved. Format 2 4 is compatible with the I S standard. Formats 5 and 6 make the STA020 look similar to existing 16- and 18-bit DACs and interpolation filters. Format 7 is an MSB-last format and is conducive to serial arithmetic. SCK and FSYNC are outputs in Format 0 and inputs in all other formats. In Format 2, the rising edge of FSYNC delineates samples and the falling edge must occur a minimum of one bit period before or after the rising edge. In all formats except 2, FSYNC contains left/right information requiring both edges of FSYNC to delineate samples. Formats 5 and 6 require a minimum of 16- or 18-bit audio words respectively. In all formats other than 5 and 6, the STA020 can accept any word length from 16 to 24 bits by adding leading zeros in format 7 and trailing zeros in the other formats, or by restricting the number of SCK periods between active edges of FSYNC to the sample word length. FSYNC must be derived from MCK, either through a DSP using the same clock or using counters. If SFYNC moves (jitters) with respect to MCK by four MCK periods, the internal counters and CBL may be reset. Table 1. Audio Port Modes
M2 0 0 0 0 1 1 1 1 M1 0 0 1 1 0 0 1 1 M0 0 1 0 1 0 1 0 1 Format 0 - FSYNC & SCK Output 1 - Left/Right, 16-24 Bits 2 - Word Sync, 16-24 Bits 3 - Reserved 4 - Left/Right, I S Compatible 5 - LSB Justified, 16 Bits 6 - LSB Justified, 18 Bits 7 - MSB Last, 16-24 Bits
2
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STA020
Figure 3. Audio Serial Port Formats.
FORMAT 0:
FSYNC(out) SCK(out) SDATA(in)
MSB LSB MSB LSB MSB LEFT RIGHT
FORMAT 1:
FSYNC(in) SCK(in) SDATA(in)
MSB LSB MSB LSB MSB LEFT RIGHT
FORMAT 2:
FSYNC(in) SCK(in) SDATA(in)
MSB LSB MSB LSB MSB LEFT RIGHT
FORMAT 3:
(RESERVED)
FORMAT 4:
FSYNC(in) SCK(in) SDATA(in)
MSB LSB MSB LSB MSB LEFT RIGHT
FORMAT 5:
FSYNC(in) SCK(in) SDATA(in) LSB
MSB 16 Bits LEFT RIGHT LSB MSB 16 Bits LSB LEFT RIGHT
FORMAT 6:
FSYNC(in) SCK(in) SDATA(in) LSB
MSB
LSB 18 Bits
MSB 18 Bits RIGHT
LSB
FORMAT 7:
FSYNC(in) SCK(in) SDATA(in) MSB
LSB LEFT
MSB
LSB
D97AU604
MSB
C, U, V Serial Port The serial input pins for channel status (C), user (U), and validity (V) are sampled during the first bit period after the active edge of FSYNC for all formats except Format 4. Format 4 is sampled during the second bit period (coincident with the MSB). In Figure 3, the arrows on SCK indicate when the C, U, and V bits are sampled. The C, U, and V bits are transmitted with the audio sample entered before FSYNC edge that sampled it. The V bit, as defined in the audio standards, is set to
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zero to indicate the audio data is suitable for conversion to analog. Therefore, when the audio data is errored, or the data is not audio, the V bit should be set high. The channel status serial input pin (C) is not available in consumer mode when the CD subcode port is enabled (FC1 = FC0 = high). Any channel status data entered through the channel status serial input (C) is logically OR'ed with the data entered through the dedicated pins or internally generated.
STA020
RST and CBL (TRNPT is low) When RST goes low, the differential line drivers are set to ground. In order to properly synchronize the ST020 to the audio serial port, the transmit timing counters, which include CBL, are not enabled after RST goes high until eight and one half SCK periods after reset is exited) of FSYNC. When FSYNC is configured as a left/right signal (all defined formats except 2), the counters and CBL are not enabled until the right sample is being transmitted). This guarantees that channel A is left and channel B is right as per the digital audio interface specs. As shown in Figure 4, channel block start output (CBL), can assist in serially inputting the C, U and V bits as CBL goes high one bit period before the first bit of the preamble of the first sub-frame of the channel status block is transmitted. This subframe contains channel status byte 0, bit 0. CBL returns low one bit period before the start of the frame that contains bit 0 of channel status byte 16. CBL is not available when the CD subcode port is enabled. Figure 4 illustrates timing for stereo data input on the audio port. Notice how CBL rises while the right channel data (Right 0) is input, but the previous left channel (Left 0) is being transmitted as the first sub-frame of the channel status block (starting with preamble Z). The C, U, and V input ports only need to be valid for a short period after FSYNC changes. A sub-frame includes one audio sample while a frame includes a stereo pair. A channel status (C.S.) block contains 24 bytes of channel status and 384 audio samples (or 192 stereo pairs, or frames, of samples). Figure 4 shows the CUV ports as having left and right bits (e.g. CUV0L, CUV0R). Since the C.S. block is defined as 192 bits, or one bit per frame, there are actually 2 C.S. blocks, one for channel A (left) and one for channel B (right). When inputting stereo audio data, both blocks normally contain the same information, so C0L and C0R from the input port pin are both channel status bit 0 of byte 0, which is defined as professional/consumer. These first two bits from the port, C0L and C0R, are logically OR'ed with the inverse PRO, since PRO is a dedicated channel status pin defined as C.S. bit 0. Also, if in professional mode, C1, C6, C7 and C9 are dedicated C.S. pins. The inverse of C1 is logically OR'ed with channel status input ports bits C1L and C1R. In similar fashion, C6, C7 and C9 are OR'ed with their respective input bits. Also, the C bits in CUV128L and CUV128R are both channel status block bit 128, which is bit 0 of channel status byte 16.
Figure 4. CBL and Transmitter Timing.
TRNPT high CBL TRNPT low
SDATA
LEFT 0
RIGHT 0
LEFT 1
LEFT 128
RIGHT 128
LEFT 0
RIGHT 0
FSYNC
C BITS FROM CPIN
TRNPT high C,U,V TRNPT low
CUV0L
CUV0R
CUV1L
CUV1R
CUV128R
CUV0L
CUV0R
CUV191R C BITS OR'ed w/PRO pin
CUV0L
CUV0R C BITS OR'ed w/C1 pin LEFT 0 RIGHT 0 VUCP0R Preamble Y
CUV1L
CUV128L BITS 0 of C.S. BLOCK BYTE 16 LEFT 128 RIGHT 128
CUV191R
CUV0L
TXP
RIGHT 191
TXN
Preamble Y VUCP191R VUCP0L Preamble Z VUCP127R
VUCP128L Preamble X Preamble Y 27 28 29 30 31
bit
0
3
4
7
8 LSB Left 0 - Audio Data SUB-FRAME
Preamble Z
Aux Data
MSB V0 U0 C0 P0
D99AU990
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STA020
Transparent Mode In certain applications it is desirable to receive digital audio data with the STA120 and retransmit it with the STA020. In this case, channel status, user and validity information must pass through unaltered. For studio environments, AES recommends that signal timing synchronization be maintained throughout the studio. Frame synchronization of digital audio signals input to and output from a piece of equipment must be within +/-5%. The transparent mode of the STA020 is selected by setting TRNPT, pin 24, high. In this mode, the CBL pin becomes an input, allowing direct connection of the outputs of the STA120 to the inputs of the STA020 as shown in Figure 18. The transmitter and receiver are synchronized by the FSYNC signal. CBL specifies the start of a new channel status block boundry, allowing the transmit block structure to be slaved to the block structure of the receiver. In the transparent mode, C, U and V are now transmitted with the current audio sample as shown in Figure 5 (TRNPT high) and the dedicated channel status pins are ignored. When FSYNC is a word clock (Format 2), CBL is sampled when left C, U, V are sampled. When FSYNC is Left/Right, CBL is sampled when left C, U, V are sampled. The channel status block boundry is reset when CBL transitions from low to high (based on two successive samples of CBL). MCK for the STA020 is normally expected to be 128 times the sample frequency, in the trasparent mode MCK must be 256 Fs. Professional Mode Setting PRO low places the STA020 in professional mode as shown in Figure 6. In professional mode, channel status bit 0 is transmitted as a one and bits 1, 2, 3, 4, 6, 7 and 9 can be controlled via dedicated pins. The pins are actually the inverse of the identified bit. For example, tying the C1 pin low places a one in channel status bit 1. As shown in the application Note, Overview of AES/EBU Digital Audio Interface Data Structures, C1 indicates audio/nonaudio; C6 and C7 determine the sample frequency and C9 allows the encoded channel mode to be stereophonic. EM1 and EM0 determine emphasis and encode C2, C3, C4 as shown in Table 2. The dedicated channel status pins are read at the appropriate time and are logically OR'ed with data input on the channel status port, C. In Transparent Mode, these dedicated channel status pins are ignored and channel status bits are input at the C pin.
Consumer Mode Setting PRO high places the STA020 in consumer mode which redefines the pins as shown in Figure 7. In consumer mode, channel status bit 0 is transmitted as a zero and channel status bits 2, 3, 8, 9, 15, 24 and 25 are controlled via dedicatedpins. The pins are actually the inverse of the bit so if pin C2 is tied high, channel status bit 2 will be transmitted as a zero. Also, FC0 and FC1 are encoded versions of channel status bits 24 and 25, which define the sample frequency. When FC0 and FC1 are both high, the part is placed in a CD submode which activates the CD subcode port. This submode is described in detail in the next section. Table 3 describes the encoding of C24 and C25 through the FC1 and FC0 pins. According to AES/EBU standards, C2 is copy prohibit/permit. C3 specifies pre-emphasis, C8 and C9 define the category code and C15 identifies the generation status of the transmitted material (i.e. first generation, second generation). Table 2. Emphasis Encoding
EM1 0 0 1 1 EM0 0 1 0 1 C2 1 1 1 0 C3 1 1 0 0 C4 1 0 0 0
Table 3. Sample Frequency Encoding
FC1 0 0 1 1 FC0 0 1 0 1 C24 0 0 1 0 C25 0 1 1 0 Comments 44.1kHz 48kHz 32kHz 44.1kHz, CD Mode
Figure 5. Transparent Mode Interface.
V+ MCK CBL C RXP U V FSYNC RXN SCK SDATA TXN TXP TRNPT
STA120
STA020
DATA PROCESSING
D97AU605
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STA020
Figure 6. Block Diagram - Professional Mode
M0 23 8 6 7 SERIAL PORT LOGIC 22 M1 21 M2
SDATA SCK FSYNC
AUDIO
AUX 20 C Bits BIPHASE MARK ENCODER LINE DRIVER 17 MUX U Bits TXN
TXP
CRC C U V 10 11 9
REGISTERS VALIDITY TIMING
16
RST
PREAMBLE
MUX
PARITY
2 PRO
14
13
3
4 C6
1 C7
12 C9 TRNPT
24
15 CBL
5 MCK
D97AU607B
EM0 EM1 C1
Figure 7. Block Diagram - Consumer Mode
M0 23 8 6 7 22
M1 21
M2
SDATA SCK FSYNC
SERIAL PORT LOGIC
AUDIO 20 BIPHASE MARK ENCODER LINE DRIVER 17 MUX TXN
AUX
TXP
C Bits C U V 10 11 9 U Bits TIMING VALIDITY
REGISTERS
16
RST
PREAMBLE
MUX
PARITY
2 PRO +3.3V
3
24
4 C2
1
13 C3 C8
14
12 C9 C15
15 CBL
5 MCK
D97AU606A
FC0 FC1
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STA020
DIM. MIN. A A1 A2 B C D E e H h k L 0.40 10.0 0.25 0.33 0.23 15.20 7.40 2.35 0.10
mm TYP. MAX. 2.65 0.30 2.55 0.51 0.32 15.60 7.60 1.27 10.65 0.75 0.394 0.010 0.013 0.009 0.598 0.291 MIN. 0.093 0.004
inch TYP. MAX. 0.104 0.012 0.100 0.0200 0.013 0.614 0.299 0,050 0.419 0.030
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 1.27 0.016 0.050
SO24
h x 45
A2
0.10mm .004 Seating Plane
B
e
A1
A
K L H
A1
C
D
24
13
1
12
SO24
10/12
E
STA020
DIM. MIN. A A1 A2 B B1 c D E E1 e e1 e2 e3 L 2.54 0.51 3.05 0.36 0.76 0.23 22.61 7.62 6.10
mm TYP. MAX. 5.08 0.020 3.30 0.46 1.02 0.25 22.86 4.57 0.56 1.14 0.38 23.11 8.64 6.40 1.778 7.62 10.92 1.52 3.30 3.81 0.10 6.86 0.120 MIN.
inch TYP. MAX. 0.20
OUTLINE AND MECHANICAL DATA
0.130
0.180
0.0142 0.0181 0.0220 0.030 0.009 0.890 0.30 0.240 0.252 0.070 0.30 0.430 0.060 0.130 0.150 0.040 0.045
0.0098 0.0150 0.90 0.910 0.340 0.270
SDIP24 (0.300")
E E1
A1
A2
Stand-off B B1 e e1 e2 c D E
24
13
F
.015 0,38 Gage Plane
1
12 e3
SDIP24
L
A
e2
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STA020
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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